DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 489

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11. Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
SDA
SCL
TRS
In a transmit operation in the slave mode of the I
or read or write to the ICCR register during the period indicated by the shaded portion
in figure 14.25.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
ICCR register, is completed before the next slave address receive operation starts.
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
Figure 14.25 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Address received
R/W
Section 14 I
8
Detection of 9th clock
cycle rising edge
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
A
9
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Waveforms if
problem occurs
2
C bus interface, do not read the ICDR register
Rev. 5.00 Sep. 01, 2009 Page 437 of 656
Data transmission
REJ09B0071-0500
Bit 7
ICDR write