DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 534

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 LCD Controller/Driver
17.4
17.4.1
To perform LCD display, the hardware and software related items described below must first be
determined.
1. Hardware Settings
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REJ09B0071-0500
A. Using 1/2 duty
B. Large-panel display
C. LCD drive power supply setting
When 1/2 duty is used, interconnect pins V
As the impedance of the built-in power supply split-resistance is large, it may not be
suitable for driving a large panel. If the display lacks sharpness when using a large panel,
refer to section 17.4.6, Boosting the LCD Drive Power Supply. When static or 1/2 duty is
selected, the common output drive capability can be increased. Set CMX to 1 when
selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output
the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and
COM1, and the COM2 waveform is output from pins COM4 and COM3.
With the H8S/2268 and 2264, there are two ways of providing LCD power: by using the
on-chip power supply circuit, or by using an external power supply circuit.
When an external power supply circuit is used for the LCD drive power supply, connect the
external power supply to the V1 pin.
Operation
Settings up to LCD Display
Figure 17.3 Handling of LCD Drive Power Supply when Using 1/2 Duty
V
V
CC
SS
2
and V
V1
V2
V3
3
as shown in figure 17.3.