DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 18

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Item
13.3.7 Serial Status
Register (SSR)
14.4.6 Slave
Transmit Operation
Rev. 5.00 Sep. 01, 2009 Page xvi of l
REJ09B0071-0500
Page
324
423
Revision (See Manual for Details)
Table amended
Note added
Notes: 2. This bit is cleared by DTC only when DISEL = 0 with
Description added
1. Initialize slave receive mode and wait for slave address
Description amended
4. The master device drives SDA low at the 9th clock pulse, and
Bit
2
reception.
returns an acknowledge signal.
When making initial settings for slave receive mode, set the
ACKE bit in ICCR to 1. This is necessary in order to enable
reception of the acknowledge bit after entering slave transmit
mode.
The master device drives SDA low at the 9th clock pulse, and
returns an acknowledge signal. This acknowledge signal is
stored in the ACKB bit in ICSR if the ACKE bit in has been
set to 1, so the ACKB bit can be used to determine whether
the transfer operation was performed successfully.
Bit Name
TEND
the transfer counter other than 0.
Initial
Value
1
R/W
R
Description
Transmit End
This bit is set to 1 when no error signal has been sent
back from the receiving end and the next transmit data is
ready to be transferred to TDR.
[Setting conditions]
The timing of bit setting differs according to the register
setting as follows:
When GM = 0 and BLK = 0, 12.5 etu after transmission
starts
When GM = 0 and BLK = 1, 11.5 etu after transmission
starts
When GM = 1 and BLK = 0, 11.0 etu after transmission
starts
When GM = 1 and BLK = 1, 11.0 etu after transmission
starts
[Clearing conditions]
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When the ERS bit is 0 and the TDRE bit is 1 after the
• When 0 is written to TDRE after reading TDRE = 1
•
specified interval following transmission of 1-byte
data.
When the DTC *
transfers transmission data to TDR (H8S/2268 Group
only)
2
is activated by a TXI interrupt and