EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 94

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

3
3-24
MaverickCrunch Co-Processor
EP93xx User’s Guide
3.5.2 Move Instructions
31:28
31:28
31:28
cond
cond
cond
Description:
Mnemonic:
Bit Definitions:
Description:
Mnemonic:
Bit Definitions:
Description:
Mnemonic:
Bit Definitions:
1 1 1 0
1 1 1 0
1 1 1 0
27:24
27:24
27:24
Move Single Precision Floating Point from ARM to MaverickCrunch
Move Single Precision Floating Point from MaverickCrunch to ARM
Move Lower Half Double Precision Float from ARM to MaverickCrunch
Moves a single precision floating point number from an ARM register into the
upper half of a MaverickCrunch register.
CFMVSR<cond> CRn, Rd
Rd:
CRn:
Moves a single precision floating point number from the upper half of a
MaverickCrunch register to an ARM register.
CFMVRS<cond> Rd, CRn
Rd:
CRn:
Moves the lower half of a double precision floating point value from an ARM
register into the lower half of a MaverickCrunch register.
CFMVDLR<cond> CRn, Rd
CRn:
Rd:
23:22
23:22
23:22
0 0
0 0
0 0
21
21
21
0
0
0
Copyright 2007 Cirrus Logic
20
20
20
0
1
0
Source ARM register
Destination register
Destination ARM register
Source register
Destination register
Source ARM register
19:16
19:16
19:16
CRn
CRn
CRn
15:12
15:12
15:12
Rd
Rd
Rd
0 1 0 0
0 1 0 0
0 1 0 0
11:8
11:8
11:8
0 1 0
0 1 0
0 0 0
7:5
7:5
7:5
4
1
4
1
4
1
DS785UM1
CRm
CRm
CRm
3:0
3:0
3:0