EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 419

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

INTERRUPT
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Channel Base Address + 0x0004 - Read/Write
This is the interrupt status register. The register is read to obtain interrupt
status for enabled interrupts. An interrupt is enabled by writing the
corresponding bits in the CONTROL register.
Write this location once to clear the interrupt. (See Interrupt Register Bit
Descriptions for the bits where this rule applies.)
RSVD:
STALLInt:
NFBInt:
ChErrorInt:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Indicates channel has stalled. This interrupt is generated
on a Channel State machine transition from ON to STALL
state, if STALLIntEn set. This is a critical interrupt as it
indicates that an over/underflow condition will occur as
soon as the peripheral’s FIFO is full/empty. The interrupt is
cleared by either disabling the channel or writing a new
base address which will move the state machine onto the
ON state.
Indicates channel requires a new buffer. This interrupt
generated on a Channel State machine transition from
NEXT to ON state if NFBIntEn set. The interrupt is cleared
by either disabling the channel or writing a new base
address, which will move the state machine onto the next
state.
This interrupt is activated when the peripheral attached to
the DMA Channel detects an error in the data stream. The
peripherals signal this error by ending the current transfer
with a TxEnd/RxEnd error response. The interrupt is
cleared by writing either a “1” or a “0” to this bit.
24
8
RSVD
23
7
22
6
21
5
20
4
ChErrorInt
19
3
EP93xx User’s Guide
18
2
0
DMA Controller
NFBInt
17
1
STALLInt
10-25
16
0
10