EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 787

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

DS785UM1
Definition:
Bit Descriptions:
In UDMA data-out and data-in operations, this register contains status about
the output and input signals, state machine status and error reporting. Several
bits reflect external pins. Their reset state can vary depending on system
implementation and system configuration.
RSVD:
CS0n:
CS1n:
DA:
HSHD:
STOP:
DM:
DDOE:
DMARQ:
DSDD:
DMAide:
INTide:
SBUSY:
NDO:
NDI:
N4X:
Copyright 2007 Cirrus Logic
Reserved. Unknown during read, ignored during write.
Chip select pin0 status. Should be driven to 1 (deasserted)
in UDMA.
Chip select pin1 status. Should be driven to 1 (deasserted)
in UDMA.
Device address status. Should be driven to 0x0 (de-
asserted) in UDMA.
HSTROBE (during data-out) and HDMARDYn (during
data-in) status. Driven by UDMA state machine.
STOP (during data-out) status. Driven by UDMA state
machine.
DMACKn (both data-out and data-in) status. Driven by
UDMA state machine.
DD bus output enable as controlled by UDMA state
machine.
Synchronized version of DMARQ input from device.
DSTROBE (during data-in) and DDMARDYn (during data-
out) status from device.
DMA request signal from UDMA state machine.
INT line generated by UDMA because of errors in the state
machine.
UDMA state machine busy, not in idle state.
Error for data-out not completed.
Error for data-in not completed.
Error for data transferred not multiples of four 32-bit words.
EP93xx User’s Guide
IDE Interface
27-17
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