EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 220

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

7
Vertical Frame Timing Registers
VLinesTotal
VSyncStrtStop
7-38
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
31
15
Address: 0x8003_0000
Default: 0x0000_0000
Definition: Total horizontal lines that compose a vertical frame
Bit Descriptions:
Address: 0x8003_0004
Default: 0x0000_0000
Definition: Vertical Sync Pulse Start/Stop register
Bit Descriptions:
30
14
30
14
RSVD
RSVD
RSVD
29
13
29
13
28
12
28
12
RSVD:
TOTAL:
RSVD:
STOP:
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
VLines Total - Read/Write
The VLines Total value written to this field specifies the
total number of horizontal lines for a video frame including
synchronization, blanking, and active lines. This value is
used to preset the Vertical down counter. Please refer to
video the signalling timing diagrams shown in
and
Reserved - Unknown during read
Stop - Read/Write
Figure
24
24
8
8
RSVD
23
23
7-10.
7
7
22
22
6
6
TOTAL
STOP
STRT
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
Figure 7-9
17
17
1
1
DS785UM1
16
16
0
0