EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 369

IC ARM9 SOC ARM920T 272TFBGA

EP9307-IRZ

Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-IRZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1256

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Part Number:
EP9307-IRZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Descriptor Processor Registers
BMCtl
DS785UM1
31
15
Soft Reset:
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
RSVD
The Descriptor Processor Registers are in three parts: the bus master control, receive
registers, and transmit registers.
30
14
MT
29
13
28
12
TT
0x0000_0000
MII Status Register
RSVD:
Busy:
0x8001_0080 - Read/Write
0x0000_0000
0x0000_0000
Bus Master Control Register
RSVD:
UnH
27
11
TxChR
26
10
Copyright 2007 Cirrus Logic
TxDis
25
9
Reserved. Unknown During Read.
MII Busy. The Busy bit is set whenever a command is
written to the MII Command Register. It is cleared when
the operation has been completed.
Reserved. Unknown During Read.
TxEn
24
8
RSVD
RSVD
23
7
EH2
22
6
EH1
21
1/10/100 Mbps Ethernet LAN Controller
5
EEOB
20
4
RSVD
19
3
EP93xx User’s Guide
RxChR
18
2
RxDis
17
1
RxEn
16
9-67
0
9

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