EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 666

IC ARM9 SOC ARM920T 272TFBGA

EP9307-IRZ

Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-IRZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1256

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Part Number:
EP9307-IRZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
21
21-10
I
EP93xx User’s Guide
21.5.2 Example of Right Justified LRCK format
21.6 Interrupts
2
S Controller
I
size = 32
I
size = 24
2
2
I
size = 16
S
2
S
SDATA
S
SCK
Figure 21-3
case and the MSB is transmitted first. The bit clock rate is 64x so the for the first 16 clock
cycles in each word there is no data as it is right justified in each word frame.
The I
combination (logical OR) of all TX and RX internal interrupts.
The transmitter generates 4 internal interrupts within the I
the status of the 3 individual TX FIFOs. These internal interrupts are as follows:
word
word
word
• TX0 FIFO empty.
• TX1 FIFO empty.
2
S controller generates a single interrupt, I2SINTR to the ARM Core. This interrupt is a
LRCKX
Bitclk
Bitclk
Bitclk
shows the frame format for Right Justified data. The word length is 16 in this
LRCKX LEFT
BCR = 64x, 32 pulses left word
Figure 21-3. Frame Format for Right Justified Data
16 pulses
Figure 21-2. Bit Clock Generation Example
15
24 pulses
..........
..........
32 pulses
Copyright 2007 Cirrus Logic
...............
2 1 0
BCR = 64x, 32 pulses right word
2
16 pulses
S controller. Each of these reflect
24 pulses
LRCKX RIGHT
..........
32 pulses
...............
..........
15
2 1 0
DS785UM1

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