EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 246

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

7
BlinkPattrn
7-64
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Bit Descriptions:
Address: 0x8003_0048
Default: 0x0000_0000
Definition: Blink Pattern register
Bit Descriptions:
30
14
29
13
28
12
RSVD:
MASK:
This register is used in conjunction with the
which pixels that are fetched from SDRAM are blink pixels (see
Register” on page
RSVD:
PATRN:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
7-33).
Reserved - Unknown during read
Mask - Read/Write
The Blink Mask value that is written to this field is logical
ANDed, ORed, or XORed with the pixel data that
addresses the LUT. The mask allows a blinking pixel to
jump from the normal color definition location to a blink
color definition location in the look-up-table.
The logical operator is selected by writing to the M field in
the
AND/OR/XOR operation can be viewed as:
ANDing modifies the LUT address by clearing bits
ORing modifies the LUT address by setting bits
XORing modifies the LUT address by inverting bits
Reserved - Unknown during read
Pattern - Read/Write
The pixel value is first operated on by the Mask field in the
BlinkMask
blink pattern value that is written to this PATRN field. If the
comparison results in a match, the pixel is validated as a
blink pixel.
PixelMode
24
8
PATRN
register. The result is then compared to the
23
7
register. The functions of the BlinkMask
22
6
21
5
BlinkMask
20
4
PATRN
register to determine
19
3
18
2
“BlinkPattrn
17
1
DS785UM1
16
0