EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 76

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

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MaverickCrunch Co-Processor
EP93xx User’s Guide
3.1.6 Comparisons
72 bits wide. If the accumulator saturation mode is disabled (the default), the accumulator bit
fields are assigned as below for a 2’s complement integer.
If the saturation mode 1.63 is selected, the bit field assignments are:
If the saturation mode 1.31 is selected, the bit field assignments are:
If the saturation mode 2.62 is selected, the bit field assignments are:
The Crunch co-processor provides four compare operations:
The DSPSC register bit UINT affects the operation of integer comparisons. If clear, integers
are treated as signed values, and if set, they are treated as unsigned. DSPSC.UINT has no
effect on floating point comparisons.
All compare operations update both the FCC[1:0] bits in the DSPSC register and an ARM
register. Though any of the ARM general purpose registers r0 through r14 may be specified
as the destination, specifying r15 actually updates the CPSR flag bits NZCV. This permits the
• CFCMP32 - 32-bit integer
• CFCMP64 - 64-bit integer
• CFCMPS - single floating point
• CFCMPD - double floating point
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Copyright 2007 Cirrus Logic
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