EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 761

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

DS785UM1
DEVINT:
PINTEN:
PENSTS:
PINT:
NICOR:
TINT:
Copyright 2007 Cirrus Logic
Deviation Interrupt. This is the deviation error interrupt.
When the DINTEN and DTMEN bits are set high and an
axis fails the deviation test 255 times causing an interrupt,
this bit must be written to a “0” to clear the interrupt.
Pen up Interrupt Enable. Setting this bit high causes an
interrupt when the algorithm first detects a pen up
condition.
Pen Status. This bit allows access to directly read the
status of the pen up / down indicator. Read only.
0 - pen up.
1 - pen down.
Pen up Interrupt. This is the Pen up interrupt. When the
PINTEN bit is set and a pen up condition is detected after
a pen down, this bit will be set high and cause the interrupt
output to go high. This bit may be written high for test
purposes and written low to clear the interrupt.
No Interrupt Clear on Read. This bit controls clearing of
the touch interrupt.
0 - TINT clears when reading TSXYResult register.
1 - The TINT bit must be written low to clear the interrupt.
Touch Interrupt. This is the touch screen activation
interrupt. When a new stable set of X and Y ADC values is
resolved, this bit will activate. It may be triggered from an
off-screen unpressed stable value. Writing a “0” to this bit
will clear the touch interrupt. This bit may be written high
for test purposes.
Analog Touch Screen Interface
EP93xx User’s Guide
25-23
25