EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 235

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

DS785UM1
CCIREN:
LCDEN:
ACEN:
INVCLK:
Copyright 2007 Cirrus Logic
V_CSYNC --> D7 (Smart Panel)
HSYNC --> D6
BLANK --> D5
P17 --> D4
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
A Smart Panel has an integrated controller and frame
buffer. Smart Panel R/W and RS signals must be
implemented via GPIOs and controlled via software.
CCIR Enable - Read/Write
The value written to this bit selects which video output
signals are generated:
0 - Normal signals
1 - CCIR656 YCrCb digital video signals
LCD Enable - Read/Write
The value written to this bit specifies the function of the
signals to the P[16] pin and P[15] pin:
0 - Pixel data bits 16 and 15 are routed to pins P16 and
P15, respectively
1 - XECL and YSCL signals are routed to pins P16 and
P15, respectively. The XECL and YSCL signals are used
to enable LCD drivers and register shifting
AC Enable - Read/Write
Writing ACEN = ‘1’ routes an LCD AC Waveform to pin
P17.
0 - Pixel data bit 17 is routed to pin P17
1 - LCD AC Wave Form is routed to pin P17. The
waveform toggles with each new vertical frame.
Invert Pixel Clock - Read/Write
The value written to this bit selects the active edge of
SPCLK on the SPCLK pin:
0 - Pixel data output changes on the rising edge of the
clock on the SPCLK pin
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7-53
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