EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 584

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

16
UART3Ctrl
16-8
UART3 With HDLC Encoder
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
BR:
0x808E_0014 - Read/Write
0x0000_0000
UART3 Control Register
RSVD:
LBE:
RTIE:
TIE:
RIE:
MSIE:
UARTE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Baud Rate Divisor bits [7:0]. Least significant byte of baud
rate divisor. These bits are cleared to 0 on reset. The baud
rate divisor is calculated as follows:
Baud rate divisor BAUDDIV = (F
rate)) –1
where F
baud rate divisor of zero is not allowed and will result in no
data transfer.
Reserved. Unknown During Read.
Loopback Enable. If this bit is set to 1, data sent to TXD is
received on RXD. This bit is cleared to 0 on reset, which
disables the loopback mode.
Receive Timeout Enable. If this bit is set to 1, the receive
timeout interrupt is enabled.
Transmit Interrupt Enable. If this bit is set to 1, the transmit
interrupt is enabled.
Receive Interrupt Enable. If this bit is set to 1, the receive
interrupt is enabled.
Modem Status Interrupt Enable. If this bit is set to 1, the
modem status interrupt is enabled.
UART Enable. If this bit is set to 1, the UART is enabled.
Data transmission and reception occurs for UART signals.
24
8
RSVD
UARTCLK
LBE
23
7
RTIE
is the UART reference clock frequency. A
22
6
TIE
21
5
RIE
20
4
UARTCLK
MSIE
19
3
/ (16 * Baud
18
2
RSVD
17
1
DS785UM1
UARTE
16
0