EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 48

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

2
2-10
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.2.8.1 Main AHB Bus Arbiter
This Main AHB Bus Arbiter controls bus master arbitration for the AHB bus. The AHB bus has
eight master interfaces:
These interfaces have an order of priority that is linked closely with the power saving modes
Halt and Standby. These power saving modes force the Arbiter to grant the default bus
master, in this case, the ARM920T.
The order of priority of the bus masters, from highest to lowest, is shown in
The priority of the arbiter may be programmed via the BusMstrArb register in the Clock and
State Controller. The arbiter can also be programmed to degrant one of these masters: DMA,
USB Host or Ethernet MAC if an interrupt (IRQ or FIQ) is pending or being serviced. This
prevents one of these masters from blocking important interrupt service routines. These
masters are thereby prevented from accessing the bus, that is, their bus requests are
masked until the IRQ/FIQ is removed (by the Interrupt Service Routine). After the IRQ/FIQ is
removed, their bus requests will again be recognized. The default is to program the arbiter so
that it does not degrant any of these masters.
In normal operation, when the ARM920T is granted the bus and a request to enter Halt mode
is received, the ARM920T is de-granted from the AHB bus. Any other master requesting the
bus during Halt mode (according to it’s priority) will be granted the bus. In the case of entry
into Standby mode, the dummy master will be granted the bus, which simply performs IDLE
transfers. In this way, all the masters except the ARM920T can be used during Halt mode, but
are shutdown upon entry into Standby mode.
• ARM920T
• DMA controller
• USB hosts (USB1, 2, 3)
• Ethernet MAC
• LCD/Raster
• Raster Hardware Cursor.
Number
Priority
1
2
3
4
5
6
(Reset value)
PRIORITY 00
Raster Cursor
ARM920T
Raster
MAC
DMA
USB
Copyright 2007 Cirrus Logic
Table 2-1. AHB Arbiter Priority Scheme
PRIORITY 01
Raster Cursor
ARM920T
Raster
MAC
DMA
USB
PRIORITY 10
Raster Cursor
ARM920T
Raster
DMA
MAC
USB
PRIORITY 11
Raster Cursor
ARM920T
Table
Raster
DMA
MAC
USB
2-1.
DS785UM1