EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 582

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

16
16-6
UART3 With HDLC Encoder
EP93xx User’s Guide
Bit Descriptions:
• UART3LinCtrlMid write, UART3LinCtrlLow write and UART3LinCtrlHigh write.
• UART3LinCtrlLow write (or UART3LinCtrlMid write) and UART3LinCtrlHigh write.
To update UART3LinCtrlLow or UART3LinCtrlMid only:
RSVD:
WLEN:
FEN:
STP2:
EPS:
PEN:
BRK:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Number of bits per frame:
11 = 8 bits
10 = 7 bits
01 = 6 bits
00 = 5 bits
FIFO Enable.
1 - Transmit and receive FIFO buffers are enabled (FIFO
mode).
0 - The FIFOs are disabled (character mode). (That is, the
FIFOs become 1-byte-deep holding registers.)
Two Stop Bits Select.
1 - Two stop bits are transmitted at the end of the frame.
0 - One stop bit is transmitted at the end of the frame.
The receive logic does not check for two stop bits being
received.
Even Parity Select.
1 - Even parity generation and checking is performed
during transmission and reception, which checks for an
even number of 1s in data and parity bits.
0 - Odd parity generation and checking is performed
during transmission and reception, which checks for an
odd number of 1s.
This bit has no effect when parity is disabled by Parity
Enable (bit 1) being cleared to 0.
Parity Enable.
1 - Parity checking and generation is enabled
0 - Parity checking is disabled and no parity bit is added to
the data frame.
Send Break.
1 - A low level is continually output on the UARTTXD
output, after completing transmission of the current
character. This bit must be asserted for at least one
complete frame transmission time in order to generate a
break condition. The transmit FIFO contents remain
unaffected during a break condition.
0 - For normal use, this bit must be cleared.
DS785UM1