EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 340

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

9
9-38
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.2.5.1 Interrupt Processing
9.2.5.2 Receive Queue Processing
9.2.5.3 Transmit Queue Processing
9.2.5.4 Other Processing
This is the suggested method for processing an interrupt:
The upper three bytes of the Interrupt Status register provide the specific information related
to the “Other” bit in the LSB. There are a number of bits that relate to the descriptor queues.
14.Wait for RxAct (BMSts) to be set, and then enqueue the receive descriptors and status.
15.Set the required values for Individual Address and Hash Table.
16.Set the required options in RXCtl and TXCtl, enabling SRxON, and STxON.
17.Set any required options in the PHY, and activate.
18.Enqueue transmit descriptors as required.
1. Interrupt received from the LAN Controller. This may be determined directly by vectoring
2. Read the Interrupt Status Clear register. Based on the result of the low byte, one or more
1. Read the RXStsQCurAdd. This is the point to which the Host needs to process the
2. Read status entries up to the value of RXStsQCurAdd.
3. For each status entry, process the receive data. Set the respective status entry to 0 after
4. Write the number of statuses processed to the RXStsEnq.
5. Write the number of descriptors returned to the RXDEnq. Writing once to each enqueue
1. Read TXStsQCurAdd. This is the point to which the Host needs to process the status
2. Read status entries up to the value of the TXStsQCurAdd.
3. For each status entry, free the data buffer.
to the interrupt service routine, or in a shared environment by polling the interrupt status
register.
status queue.
queue.
This will trigger bus master activity for the descriptor reads.
of three processes need to run - receive queue processing, transmit queue processing,
or other processing.
the data has been processed
register is more economical on bus cycles than writing once for every descriptor or
status entry. Writing once also avoids any possible delays that may otherwise occur
when the controller has to process multiple accesses to the same descriptor.
Copyright 2007 Cirrus Logic
DS785UM1