EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 269

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

DS785UM1
8.4.1 Memory Organization for 1 Bit Per Pixel (bpp)
8.4.2 Memory Organization for 4-Bits Per Pixel
8.4.3 Memory Organization for 8-Bits Per Pixel
The 1 bpp storage format is for storing compressed image data for remapping only. This data
cannot be displayed until it is remapped into a supported color depth.
compressed 1 bpp images are stored in memory as 8 pixels per byte.
The 4 bpp storage format can be used to support monochrome, 8 levels of grayscale, and 8
or 16 color displays. The actual frame buffer can be organized as 2 pixels per byte or 1 pixel
per byte. The Graphics Accelerator engine treats 4 bpp with 1 pixel per byte as 8 bpp mode.
Table 8-3
The 8 bpp storage format can be used to support 8 level grayscale and color displays. For
color displays, this mode would use a software changeable palette in the Raster Engine to
map 256 color selections to 24-bit colors.
memory as 1 pixel per byte.
0x0000
0x0004
0x0008
0x0000
0x0004
0x0008
0x0000
0x0004
shows how 4 bpp images are stored in memory as 2 pixels per byte.
31
31
P(7,3)....... ......P(0,3) P(7,2)....... ......P(0,2) P(7,1)....... ......P(0,1) P(7,0)....... ......P(0,0)
X
P(6,0)
P(6,1)
P(6,2)
P(6,3)
P(6,4)
P(6,5)
28 27
P(7,0)
P(7,1)
P(7,2)
P(7,3)
P(7,4)
P(7,5)
Table 8-3. 4 bpp Memory Organization
Table 8-2. bpp Memory Organization
24 23
X X
24 23
Copyright 2007 Cirrus Logic
P(4,0)
P(4,1)
P(4,2)
P(4,3)
P(4,4)
P(4,5)
20 19
Table 8-4
P(5,0)
P(5,1)
P(5,2)
P(5,3)
P(5,4)
P(5,5)
16 15
X P(7,5)....... ......P(0,5) P(7,4)....... ......P(0,4)
16 15
P(2,0)
P(2,1)
P(2,2)
P(2,3)
P(2,4)
P(2,5)
shows how 8 bpp images are stored in
12 11
P(3,0)
P(3,1)
P(3,2)
P(3,3)
P(3,4)
P(3,5)
8 7
8 7
P(0,0)
P(0,1)
P(0,2)
P(0,3)
P(0,4)
P(0,5)
Table 8-2
4 3
Graphics Accelerator
EP93xx User’s Guide
P(1,0)
P(1,1)
P(1,2)
P(1,3)
P(1,4)
P(1,5)
shows how
0
0
8-5
8