EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 158

• Manufacturer Part Number: EP9307-IRZ
• Description: IC ARM9 SOC ARM920T 272TFBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-IRZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 272-TFBGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 14
• Ram Memory Size: 32MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: TFBGA
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1256

5
KeyTchClkDiv
5-32
System Controller
EP93xx User’s Guide
TSEN
KEN
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
SDIV:
MENA:
ESEL:
PSEL:
PDIV:
MDIV:
0x8093_0090 - Read/Write, Software locked
0x0000_0000
Configures the Key Matrix, Touchscreen, and ADC clocks. Touchscreen clock
is a fixed divide-by-4 from the ADC clock. Touch Filter clock is a fixed divide-
by-2 from the ADC clock.
RSVD:
TSEN:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
SCLK divide select.
1 - SCLK = MCLK / 4,
0 - SCLK = MCLK / 2.
Enable master clock generation.
External clock source select.
0 - Use the external XTALI clock input as the clock source.
1 - Use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - Select PLL2 as the clock source.
0 - Select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
MCLK divider value. Forms a divide-by-N of the pre-divide
clock output. MCLK is the source clock divided by PDIV
divided by N.
Reserved. Unknown During Read.
Touchscreen and ADC clock enable
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
ADIV
KDIV
16
0