ATMEGA168-15AZ Atmel, ATMEGA168-15AZ Datasheet - Page 65

• Manufacturer Part Number: ATMEGA168-15AZ
• Description: MCU AVR 16K FLASH 15MHZ 32-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA168-15AZ

• Package / Case: 32-TQFP, 32-VQFP
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 23
• Eeprom Size: 512 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Program Memory Size: 16KB (16K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: 2-Wire/USART/Serial
• Total Internal Ram Size: 1KB
• # I/os (max): 23
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.2.3
10.2.4
7530I–AVR–02/10
Switching Between Input and Output
Reading the Pin Value
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 10-1
Table 10-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay.
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
DDxn
0
0
0
1
1
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PORTxn
summarizes the control signals for the pin value.
0
1
1
0
1
Port Pin Configurations
PINxn
r17
(in MCUCR)
PUD
X
X
X
0
1
Figure
XXX
Output
Output
ATmega48/88/168 Automotive
Input
Input
Input
10-2, the PINxn Register bit and the preceding latch con-
I/O
pd,max
t
pd, max
Pull-up
and t
0x00
Yes
No
No
No
No
XXX
pd,min
t
pd, min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
respectively.
Figure 10-3
in r17, PINx
shows a timing dia-
0xFF
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