ATMEGA168-15AZ Atmel, ATMEGA168-15AZ Datasheet - Page 18

MCU AVR 16K FLASH 15MHZ 32-TQFP

ATMEGA168-15AZ

Manufacturer Part Number
ATMEGA168-15AZ
Description
MCU AVR 16K FLASH 15MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA168-15AZ

Package / Case
32-TQFP, 32-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
23
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
1K x 8
Program Memory Size
16KB (16K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
I²C, SPI, UART/USART
Core Size
8-Bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
2-Wire/USART/Serial
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA168-15AZ
Manufacturer:
Atmel
Quantity:
10 000
5.3.1
5.3.2
5.3.3
18
ATmega48/88/168 Automotive
EEPROM Read/Write Access
The EEPROM Address Register – EEARH and EEARL
The EEPROM Data Register – EEDR
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
• Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
256/512/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0
and 255/511/511. The initial value of EEAR is undefined. A proper value must be written before
the EEPROM may be accessed.
EEAR8 is an unused bit in ATmega48 and must always be written to zero.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
“Preventing EEPROM Corruption” on page 22
CC
is likely to rise or fall slowly on power-up/down. This causes the device for some
EEAR7
MSB
R/W
R/W
15
R
7
0
X
7
0
EEAR6
R/W
R/W
14
R
X
6
0
6
0
EEAR5
R/W
R/W
13
R
X
5
0
5
0
EEAR4
R/W
R/W
12
R
4
0
X
4
0
for details on how to avoid problems in these
EEAR3
Table
R/W
R/W
11
R
X
3
0
3
0
5-2. A self-timing function, however,
EEAR2
R/W
R/W
10
R
X
2
0
2
0
EEAR1
R/W
R/W
R
9
1
0
X
1
0
EEAR8
EEAR0
R/W
LSB
R/W
R/W
X
X
8
0
0
0
7530I–AVR–02/10
EEARH
EEARL
EEDR

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