ATMEGA168-15AZ Atmel, ATMEGA168-15AZ Datasheet - Page 163
![MCU AVR 16K FLASH 15MHZ 32-TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA168-15AZ
Manufacturer Part Number
ATMEGA168-15AZ
Description
MCU AVR 16K FLASH 15MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA168-15AZ.pdf
(340 pages)
Specifications of ATMEGA168-15AZ
Package / Case
32-TQFP, 32-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
23
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
1K x 8
Program Memory Size
16KB (16K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
I²C, SPI, UART/USART
Core Size
8-Bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
2-Wire/USART/Serial
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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16.1.4
16.1.5
16.2
7530I–AVR–02/10
Data Modes
SPI Status Register – SPSR
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
or lower.
The SPI interface on the ATmega48/88/168 is also used for program memory and EEPROM
downloading or uploading. See
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
16-3
nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
Table 16-2
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
and
Figure
and
Table
MSB
SPIF
R/W
16-4. Data bits are shifted out and latched in on opposite edges of the SCK sig-
R
X
7
0
7
16-3, as done below.
Table
WCOL
R/W
6
X
R
6
0
16-4). This means that the minimum SCK period will be two CPU
page 293
R/W
5
X
R
5
–
0
ATmega48/88/168 Automotive
for serial programming and verification.
R/W
4
X
R
4
–
0
R/W
3
X
R
3
–
0
R/W
X
2
R
2
–
0
R/W
X
1
R
1
–
0
SPI2X
LSB
R/W
R/W
X
0
0
0
Undefined
SPDR
SPSR
Figure
osc
163
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