ATMEGA168-15AZ Atmel, ATMEGA168-15AZ Datasheet

MCU AVR 16K FLASH 15MHZ 32-TQFP

ATMEGA168-15AZ

Manufacturer Part Number
ATMEGA168-15AZ
Description
MCU AVR 16K FLASH 15MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA168-15AZ

Package / Case
32-TQFP, 32-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
23
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
1K x 8
Program Memory Size
16KB (16K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
I²C, SPI, UART/USART
Core Size
8-Bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
2-Wire/USART/Serial
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA168-15AZ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA168-15AZ
Manufacturer:
ATMEL
Quantity:
8 456
Features
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Temperature Range:
Speed Grade:
Low Power Consumption
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 4/8/16K Bytes of In-System Self-Programmable Flash (ATmega48/88/168)
– Optional Boot Code Section with Independent Lock Bits
– 256/512/512 Bytes EEPROM (ATmega48/88/168)
– 512/1K/1K Byte Internal SRAM (ATmega48/88/168)
– Programming Lock for Software Security
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
– 23 Programmable I/O Lines
– Green/ROHS 32-lead TQFP and 32-pad QFN
– 2.7 - 5.5V for ATmega48/88/168
– -40
– ATmega48/88/168: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
– Active Mode:
– Power-down Mode:
Mode
Standby
• Endurance: 75,000 Write/Erase Cycles
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
• Endurance: 100,000 Write/Erase Cycles
• 4 MHz, 3.0V: 1.8mA
• 5µA at 3.0V
°
C to 125
°
C
®
8-Bit Microcontroller
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
ATmega48
ATmega88
ATmega168
Automotive
7530I–AVR–02/10

Related parts for ATMEGA168-15AZ

ATMEGA168-15AZ Summary of contents

Page 1

... ATmega48/88/168 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Low Power Consumption – Active Mode: • 4 MHz, 3.0V: 1.8mA – Power-down Mode: • 5µA at 3.0V ® 8-Bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System Programmable Flash ATmega48 ATmega88 ATmega168 Automotive 7530I–AVR–02/10 ...

Page 2

Pin Configurations Figure 1-1. Pinout ATmega48/88/168 TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 1.1 Disclaimer Typical values contained in this datasheet are based ...

Page 3

Block Diagram Figure 2-1. 7530I–AVR–02/10 ATmega48/88/168 Automotive Block Diagram Watchdog Power Timer Supervision POR / BOD & Watchdog RESET Oscillator Oscillator Flash Circuits / Clock Generation EEPROM 8bit T/C 0 16bit T/C 1 Analog 8bit T/C 2 Comp. USART ...

Page 4

... Evaluation kits. 2.2 Automotive Quality Grade The ATmega48-15AZ, ATmega88-15AZ and ATmega168-15AZ have been developed and man- ufactured according to the most stringent requirements of the international standard ISO-TS-16949 grade 1. This data sheet contains limit values extracted from the results of exten- sive characterization (Temperature and Voltage). The quality and reliability of the ATmega48-15AZ, ATmega88-15AZ and ATmega168-15AZ have been verified during regular product qualification as per AEC-Q100 ...

Page 5

... Table 2-1. Temperature -40 ; +85 -40 ; +105 -40 ; +125 2.3 Comparison Between ATmega48, ATmega88, and ATmega168 The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support, and interrupt vector sizes. for the three devices. Table 2-2. Device ATmega48 ATmega88 ATmega168 ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. ...

Page 6

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 ...

Page 7

About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all ...

Page 8

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being ...

Page 9

ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate ...

Page 10

Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z ...

Page 11

The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...

Page 12

Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 vard architecture and the fast-access Register ...

Page 13

... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see and ATmega168” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...

Page 14

... Since all AVR instructions are bits wide, the Flash is orga- nized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Loader Section and Application Program Section in ATmega88 and ATmega168. ATmega48 does not have separate Boot Loader and Application Program sections, and the SPM instruction can be executed from the entire Flash. See SELFPRGEN description in section “ ...

Page 15

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in ing” on page Figure 5-1. 7530I–AVR–02/10 ATmega48/88/168 Automotive 12. ...

Page 16

... SRAM in the ATmega48/88/168 are all accessible through all these addressing modes. The Register File is described in ter File” on page ATmega48/88/168 Automotive 16 Program Memory Map, ATmega88 and ATmega168 Program Memory Application Flash Section Boot Flash Section shows how the ATmega48/88/168 SRAM Memory is organized. ...

Page 17

Figure 5-3. 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 5-4. 5.3 EEPROM Data Memory The ATmega48/88/168 contains 256/512/512 bytes ...

Page 18

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in lets the user software detect when the next byte can be written. If the user code ...

Page 19

The EEPROM Control Register – EECR Bit Read/Write Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: ...

Page 20

... Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See Support – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 263 details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out ...

Page 21

Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no ...

Page 22

Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 5.3.5 Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as ...

Page 23

I/O Memory The I/O space definition of the ATmega48/88/168 is shown in All ATmega48/88/168 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...

Page 24

System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 25

Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...

Page 26

Table 6-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual voltage and it will be required to select a delay ...

Page 27

Figure 6-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in on page Table 6-3. Frequency Range Notes: The ...

Page 28

Table 6-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 6.4 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier ...

Page 29

Figure 6-3. Table 6-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast ...

Page 30

Low Frequency Crystal Oscillator The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Fre- quency Crystal Oscillator. The crystal should be connected as shown in Oscillator is selected, start-up times are determined ...

Page 31

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-9 on page Table 6-9. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 6.6.1 Oscillator Calibration Register – OSCCAL Bit ...

Page 32

Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by ...

Page 33

Figure 6-4. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-13. Table 6-13. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock ...

Page 34

Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to logic one. See tion on selecting external clock as input instead kHz crystal. 6.11 System Clock Prescaler The ATmega48/88/168 has a system ...

Page 35

Clock Prescale Register – CLKPR Bit Read/Write Initial Value • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only ...

Page 36

Table 6-14. CLKPS3 7. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion ...

Page 37

Table 7-1. SM2 Note: • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the ...

Page 38

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to for details. When waking up from Power-down mode, there is ...

Page 39

Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripher- als to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read ...

Page 40

Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...

Page 41

... During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATmega168, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48 and ATmega88, the instruction placed at the Reset Vector must be an RJMP – ...

Page 42

Reset Sources The ATmega48/88/168 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...

Page 43

Figure 8- TIME-OUT INTERNAL RESET Figure 8-3. V RESET TIME-OUT INTERNAL RESET Table 8-1. Symbol V POT V PORMAX V PORMIN V CCRR V RST Note: 7530I–AVR–02/10 ATmega48/88/168 Automotive MCU Start-up, RESET Tied CCRR V ...

Page 44

External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches ...

Page 45

Table 8-3. Symbol V HYST t BOD When the BOD is enabled, and V 8-5), the Brown-out Reset is immediately activated. When V (V BOT+ expired. The BOD circuit will only detect a drop in V ger than t Figure ...

Page 46

MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/Write Initial Value • Bit 7..4: Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will ...

Page 47

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power ...

Page 48

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for ...

Page 49

Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. ...

Page 50

Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching ...

Page 51

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding ...

Page 52

... Each Interrupt Vector occupies two instruction words in ATmega168, and one instruction word in ATmega48 and ATmega88. • ATmega48 does not have a separate Boot Loader Section. In ATmega88 and ATmega168, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR ...

Page 53

Interrupt Vectors in ATmega48 Table 9-1. Vector No The most typical and general ...

Page 54

Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 ; 0x01ARESET: 0x01B 0x01C 0x01D 0x01E 0x01F ... 9.2 Interrupt Vectors ...

Page 55

... When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 263. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section ...

Page 56

Table 9-3. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88 is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F ...

Page 57

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset ...

Page 58

... ATmega48/88/168 Automotive 58 RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx Reset and Interrupt Vectors in ATmega168 Program (2) Address Source Interrupt Definition External Pin, Power-on Reset, Brown-out Reset and Watchdog (1) 0x0000 RESET System Reset 0x0002 INT0 ...

Page 59

... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in ATmega168 IVSEL Reset Address 1 ...

Page 60

... When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168 is: Address Labels Code .org 0x0002 0x0002 0x0004 ... ...

Page 61

... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168 is: Address Labels Code ...

Page 62

... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 263 Boot Lock bits. ; Enable change of Interrupt Vectors ldi r16, (1< ...

Page 63

Figure 10-1. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” repre- sents the numbering letter for the port, and a lower case “n” represents the bit number. ...

Page 64

Figure 10-2. General Digital I/O Note: 10.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Description for I/O Ports” on page PORTxn bits at the PORTx I/O address, and the ...

Page 65

Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must ...

Page 66

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...

Page 67

Assembly Code Example C Code Example unsigned char i; Note: 10.2.5 Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save ...

Page 68

Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...

Page 69

Note: Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate ...

Page 70

MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...

Page 71

PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source. If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0. • XTAL1/TOSC1/PCINT6 – Port B, Bit 6 XTAL1: ...

Page 72

OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1B pin ...

Page 73

Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 7530I–AVR–02/10 ATmega48/88/168 Automotive Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ ...

Page 74

Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 10-6. Port Pin The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL ...

Page 75

SDA/ADC4/PCINT12 – Port C, Bit 4 SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O ...

Page 76

Table 10-7 shown in Table 10-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 10-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega48/88/168 Automotive 76 and Table 10-8 relate ...

Page 77

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-9. Port Pin The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure ...

Page 78

T1/OC0B/PCINT21 – Port D, Bit 5 T1, Timer/Counter1 counter source. OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an ...

Page 79

Table 10-10. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 10-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...

Page 80

Register Description for I/O Ports 10.4.1 The Port B Data Register – PORTB Bit Read/Write Initial Value 10.4.2 The Port B Data Direction Register – DDRB Bit Read/Write Initial Value 10.4.3 The Port B Input Pins Address – PINB ...

Page 81

The Port D Input Pins Address – PIND Bit Read/Write Initial Value 11. External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will ...

Page 82

Table 11-1. ISC11 • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the ...

Page 83

Bit 0 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled. The Interrupt Sense Control0 bits ...

Page 84

Bit 1 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT14..8 ...

Page 85

Pin Change Mask Register 2 – PCMSK2 Bit Read/Write Initial Value • Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16 Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is set ...

Page 86

Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: 12.1 ...

Page 87

Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case ...

Page 88

Figure 12-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...

Page 89

Figure 12-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

Page 90

The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in ...

Page 91

Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...

Page 92

Figure 12-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

Page 93

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...

Page 94

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of ...

Page 95

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to ...

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Figure 12-9 Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 12-10 mode and PWM mode, where OCR0A is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn ...

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Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...

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Table 12-3 rect PWM mode. Table 12-3. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...

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Table 12-6 rect PWM mode. Table 12-6. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM01:0: ...

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Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...

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Table 12-8. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

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Timer/Counter Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare ...

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Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one ...

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Figure 13-1. T1/T0 Pin Sampling Tn The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling ...

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General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the ...

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Figure 14-1. 16-bit Timer/Counter Block Diagram Note: 14.1.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described ...

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The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Coun- ter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output ...

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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...

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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned ...

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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...

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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...

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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 14.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...

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The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGM13:0) bits must be set before the TOP ...

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Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the ...

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The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...

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Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...

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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register ...

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Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared ...

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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its ...

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When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a ...

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Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, ...

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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord- ingly at the same timer clock cycle ...

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Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13 provides a high resolution phase and frequency correct PWM wave- form generation option. ...

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Figure 14-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). ...

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The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set ...

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Figure 14-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that ...

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Timer/Counter Register Description 14.10.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 ...

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Table 14-3 correct or the phase and frequency correct, PWM mode. Table 14-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of ...

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Table 14- Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the location of these bits are compatible with ...

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Timer/Counter1 Control Register B – TCCR1B Bit Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from ...

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If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 14.10.3 Timer/Counter1 Control Register C ...

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Output Compare Register 1 A – OCR1AH and OCR1AL Bit Read/Write Initial Value 14.10.6 Output Compare Register 1 B – OCR1BH and OCR1BL Bit Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared ...

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Bit 4, 3 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to ...

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Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe ...

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Figure 15-1. 8-bit Timer/Counter Block Diagram 15.1.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts ...

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Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise ...

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Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22 the timer is stopped. However, ...

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The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of ...

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Figure 15-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input ...

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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode ...

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An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to ...

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Figure 15-6. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the ...

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Phase Correct PWM Mode The phase correct PWM mode (WGM22 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...

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In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to ...

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Figure 15-9 Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 15-10 Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 Figure 15-11. Timer/Counter Timing ...

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Timer/Counter Register Description 15.8.1 Timer/Counter Control Register A – TCCR2A Bit Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of ...

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Table 15-3 rect PWM mode. Table 15-3. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits ...

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Table 15-6 rect PWM mode. Table 15-6. COM2B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM21:0: ...

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Timer/Counter Control Register B – TCCR2B Bit Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...

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Table 15-8. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

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Timer/Counter2 Interrupt Mask Register – TIMSK2 Bit Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set ...

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Asynchronous operation of the Timer/Counter 15.9.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be ...

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When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the ...

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Asynchronous Status Register – ASSR Bit Read/Write Initial Value • Bit 6 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an ...

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Timer/Counter Prescaler Figure 15-12. Prescaler for Timer/Counter2 PSRASY The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is ...

Page 156

Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48/88/168 and peripheral devices or between several AVR devices. The ATmega48/88/168 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer ...

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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...

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Table 16-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction ...

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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 7530I–AVR–02/10 ATmega48/88/168 Automotive (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, ...

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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: ATmega48/88/168 Automotive 160 ...

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SS Pin Functionality 16.1.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...

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When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written ...

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SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and ...

Page 164

Table 16-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 ATmega48/88/168 Automotive 164 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample ...

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USART0 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master ...

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Figure 17-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...

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Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in ...

Page 168

Table 17-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f ...

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External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...

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Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as ...

Page 171

Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits ...

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Assembly Code Example USART_Init: C Code Example void USART_Init( unsigned int baud ) { } Note: More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a ...

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Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The ...

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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCSRnB before the low byte of the character is written to UDRn. The following ...

Page 175

Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether ...

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Receiving Frames with Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCKn clock, and shifted ...

Page 177

Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...

Page 178

Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

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Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par- ity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker ...

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Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, ...

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The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure ...

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slow Table 17-2 that Normal Speed mode has higher toleration of baud rate variations. Table 17-2. # (Data+Parity Bit) Table 17-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the ...

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Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the ...

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USART Register Description 17.9.1 USART I/O Data Register n– UDRn Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...

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Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is ...

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Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper- ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating ...

Page 187

Receiver will generate a parity value for the incoming data and compare it to the UPMn setting mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 17-5. • Bit 3 – USBSn: Stop Bit Select ...

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USART Baud Rate Registers – UBRRnL and UBRRnH Bit Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH ...

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Table 17-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc U2Xn = 0 Baud Rate UBRR UBRR (bps) n Error n 57.6k 0 8.5% 1 76.8k – – 1 115.2k – – 0 230.4k ...

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Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc U2Xn = 0 Baud Rate UBRR UBRR (bps) n Error n 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 ...

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Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc U2Xn = 0 U2Xn = 1 Baud Rate UBRR UBRR (bps) n Error n 2400 416 -0.1% 832 4800 207 0.2% 416 9600 ...

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USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow- ing features: • Full Duplex, Three-wire ...

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Note: BAUD f UBRRn 18.3 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are ...

Page 194

The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for ...

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Assembly Code Example USART_Init: C Code Example void USART_Init( unsigned int baud ) { } Note: 7530I–AVR–02/10 ATmega48/88/168 Automotive (1) clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ...

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Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin ...

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Assembly Code Example USART_MSPIM_Transfer: USART_MSPIM_Wait_RXCn: C Code Example unsigned char USART_Receive( void ) { } Note: 18.5.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in ...

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USART MSPIM Register Description The following section describes the registers used for SPI operation using the USART. 18.6.1 USART MSPIM I/O Data Register - UDRn The function and bit description of the USART data register (UDRn) in MSPI mode ...

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Bit 6 - TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt ...

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Bit 5:3 - Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 - ...

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