ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 87

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8127E–AVR–11/11
switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the
ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles, as summarised in
first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock
cycles in order to initialize the analog circuitry. See
Figure 13-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 3 ADC clock cycles after the start of a normal conver-
sion and 16 ADC clock cycles after the start of a first conversion. See
conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Sin-
gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again,
and a new conversion will be initiated on the first rising ADC clock edge.
Figure 13-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See
13-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode,
the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCL
Update
MUX
Update
MUX
1
1
2
2
12
Sample & Hold
3
13
4
14
5
15
Sample & Hold
6
16
First Conversion
7
17
One Conversion
18
8
Figure
19
9
20
13-4.
10
21
11
22
Table 13-1 on page
ATtiny4/5/9/10
12
23
Conversion
Complete
24
13
Figure
Conversion
Complete
25
Update
MUX
13-5. When a
Conversion Result
Update
Next Conversion
MUX
1
Conversion Result
Next
Conversion
1
2
88. The
2
Figure
3
3
87