ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 34

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.4.2
34
ATtiny4/5/9/10
VLMCSR – V
CC
• Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 8-3 on page
Table 8-3.
• Bit 7 – VLMF: VLM Flag
This bit is set by the VLM circuit to indicate that a voltage level condition has been triggered (see
Table
age at V
• Bit 6 – VLMIE: VLM Interrupt Enable
When this bit is set the VLM interrupt is enabled. A VLM interrupt is generated every time the
VLMF flag is set.
• Bits 5:3 – Res: Reserved Bits
These bits are reserved. For ensuring compatibility with future devices, these bits must be writ-
ten to zero, when the register is written.
Level Monitoring Control and Status register
Bit
0x34
Read/Write
Initial Value
WDP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8-4). The bit is cleared when the trigger level selection is set to “Disabled”, or when volt-
CC
WDP2
rises above the selected trigger level.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VLMF
Watchdog Timer Prescale Select
R
7
0
34.
WDP1
VLMIE
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
6
0
WDP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
–
R
0
R
4
–
0
1024K (1048576) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
Oscillator Cycles
Number of WDT
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
R
3
–
0
VLM2
R/W
2
0
Reserved
VLM1
R/W
1
0
Typical Time-out at
VLM0
R/W
0
0
V
CC
0.125 s
16 ms
32 ms
64 ms
0.25 s
0.5 s
1.0 s
2.0 s
4.0 s
8.0 s
= 5.0V
VLMCSR
8127E–AVR–11/11