ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 103

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.5
14.5.1
14.5.2
8127E–AVR–11/11
Instruction Set
SLD - Serial LoaD from data space using indirect addressing
SST - Serial STore to data space using indirect addressing
The TPI has a compact instruction set that is used to access the TPI Control and Status Space
(CSS) and the data space. The instructions allow the external programmer to access the TPI,
the NVM Controller and the NVM memories. All instructions except SKEY require one byte oper-
and following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions
are byte-sized.
The TPI instruction set is summarised in
Table 14-1.
The SLD instruction uses indirect addressing to load data from the data space to the TPI physi-
cal layer shift-register for serial read-out. The data space location is pointed by the Pointer
Register (PR), where the address must have been stored before data is accessed. The Pointer
Register is either left unchanged by the operation, or post-incremented, as shown in
Table 14-2.
The SST instruction uses indirect addressing to store into data space the byte that is shifted into
the physical layer shift register. The data space location is pointed by the Pointer Register (PR),
Mnemonic
SLD
SLD
SST
SST
SSTPR
SIN
SOUT
SLDCS
SSTCS
SKEY
Operation
data
data
←
←
DS[PR]
DS[PR]
Instruction Set Summary
The Serial Load from Data Space (SLD) Instruction
Operand
data, PR
data, PR+
PR, data
PR+, data
PR, a
data, a
a, data
data, a
a, data
Key, {8{data}}
Opcode
0010 0000
0010 0100
Description
Serial LoaD from data space using indirect
addressing
Serial LoaD from data space using indirect
addressing and post-increment
Serial STore to data space using indirect
addressing
Serial STore to data space using indirect
addressing and post-increment
Serial STore to Pointer Register using direct
addressing
Serial IN from data space
Serial OUT to data space
Serial LoaD from Control and Status space
using direct addressing
Serial STore to Control and Status space
using direct addressing
Serial KEY
Table
14-1.
Remarks
PR
PR
←
←
PR
PR + 1
ATtiny4/5/9/10
Register
Unchanged
Post increment
data
Key
Operation
data
data
PR
DS[PR]
DS[PR]
PR
PR[a]
I/O[a]
data
CSS[a]
←
←
←
←
←
←
←
←
←
PR+1
PR+1
←
{8{data}}
←
←
DS[PR]
DS[PR]
I/O[a]
CSS[a]
Table
data
data
data
data
data
14-2.
103