ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 16

no-image

ATtiny5

Manufacturer Part Number
ATtiny5
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny5

Flash (kbytes)
0.5 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
8
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATtiny5-TS8R
Manufacturer:
Atmel
Quantity:
8 105
Part Number:
ATtiny5-TSHR
Manufacturer:
OMRON
Quantity:
1 500
Part Number:
ATtiny5-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATtiny5-TSHR
Quantity:
12 000
Part Number:
ATtiny55V-10SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
5.3
I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in
“Register Summary” on page
150.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed using the LD and ST instructions, enabling data transfer between the 16 general pur-
pose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F
are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of sin-
gle bits can be checked by using the SBIS and SBIC instructions. See document “AVR
Instruction Set” and section
“Instruction Set Summary” on page 152
for more details. When
using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such status flags. The CBI and SBI instructions work on registers in the address range 0x00
to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.
ATtiny4/5/9/10
16
8127E–AVR–11/11

Related parts for ATtiny5