ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 77

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.11.3
8127E–AVR–11/11
TCCR0C – Timer/Counter0 Control Register C
When a capture is triggered according to the ICES0 setting, the counter value is copied into the
Input Capture Register (ICR0). The event will also set the Input Capture Flag (ICF0), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR0 is used as TOP value (see description of the WGM03:0 bits located in the
TCCR0A and the TCCR0B Register), the ICP0 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR0B is written.
• Bits 4:3 – WGM03:2: Waveform Generation Mode
See
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits set the clock source to be used by the Timer/Counter, see
12
Table 11-6.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC0A: Force Output Compare for Channel A
• Bit 6 – FOC0B: Force Output Compare for Channel B
The FOC0A/FOC0B bits are only active when the WGM03:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR0A is written when operating in a PWM mode. When writing a logical one to the
FOC0A/FOC0B bit, an immediate compare match is forced on the Waveform Generation unit.
Bit
0x2C
Read/Write
Initial Value
CS02
and
0
0
0
0
1
1
1
1
“TCCR0A – Timer/Counter0 Control Register A” on page
Figure
CS01
11-13.
0
0
1
1
0
0
1
1
Clock Select Bit Description
FOC0A
W
7
0
CS00
FOC0B
0
1
0
1
0
1
0
1
W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T0 pin. Clock on falling edge
External clock source on T0 pin. Clock on rising edge
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R
4
–
0
R
3
–
0
74.
R
2
–
0
ATtiny4/5/9/10
R
1
–
0
R
0
–
0
Figure 11-
TCCR0C
77