ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 14

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5. Memories
5.1
5.2
14
In-System Re-programmable Flash Program Memory
Data Memory
ATtiny4/5/9/10
This section describes the different memories in the ATtiny4/5/9/10. Devices have two main
memory areas, the program memory space and the data memory space.
The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash mem-
ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized
as 256/512 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny4/5/9/10
Program Counter (PC) is 9 bits wide, thus capable of addressing the 256/512 program memory
locations, starting at 0x000.
on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory. Since pro-
gram memory can not be accessed directly, it has been mapped to the data memory. The
mapped program memory begins at byte address 0x4000 in data memory (see
page
must be addressed starting from 0x4000 when accessed via the data memory.
Internal write operations to Flash program memory have been disabled and program memory
therefore appears to firmware as read-only. Flash memory can still be written to externally but
internal write operations to the program memory area will not be succesful.
Timing diagrams of instruction fetch and execution are presented in
ing” on page
Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile
memory lock bits, and the Flash memory. See
the ATtiny4/5/9/10 memory space is organized.
The first 64 locations are reserved for I/O memory, while the following 32 data memory locations
address the internal data SRAM.
The non-volatile memory lock bits and all the Flash memory sections are mapped to the data
memory space. These locations appear as read-only for device firmware.
The four different addressing modes for data memory are direct, indirect, indirect with pre-decre-
ment, and indirect with post-increment. In the register file, registers R26 to R31 function as
pointer registers for indirect addressing.
The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using
the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF.
The indirect addressing reaches the entire data memory space. When using indirect addressing
modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are
decremented or incremented.
15). Although programs are executed starting from address 0x000 in program memory it
9.
“Memory Programming” on page 108
Figure 5-1 on page 15
contains a detailed description
“Instruction Execution Tim-
for an illustration on how
Figure 5-1 on
8127E–AVR–11/11