ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 22

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.5.3
22
ATtiny4/5/9/10
CLKPSR – Clock Prescale Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written at run-time to vary the clock frequency and suit the application
requirements. As the prescaler divides the master clock input to the MCU, the speed of all syn-
chronous peripherals is reduced accordingly. The division factors are given in
Table 6-4.
To avoid unintentional changes of clock frequency, a protected change sequence must be fol-
lowed to change the CLKPS bits:
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected
clock source has a frequency higher than the maximum allowed the application software must
make sure a sufficient division factor is used. To make sure the write procedure is not inter-
rupted, interrupts must be disabled when changing prescaler settings.
Bit
0x36
Read/Write
Initial Value
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
R
7
–
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
R
5
–
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R
4
–
0
CLKPS3
R/W
3
0
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKPS2
R/W
2
0
CLKPS1
R/W
1
1
Clock Division Factor
CLKPS0
8 (default)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
0
1
128
256
16
32
64
Table
1
2
4
8127E–AVR–11/11
CLKPSR
6-4.