ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 42

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ATtiny5

Manufacturer Part Number
ATtiny5
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny5

Flash (kbytes)
0.5 Kbytes
Pin Count
6
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
1
Hardware Qtouch Acquisition
No
Max I/o Pins
4
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
8
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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10.2
10.2.1
42
Ports as General Digital I/O
ATtiny4/5/9/10
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O
Note:
Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in
“Register Description” on page
PORTxn bits at the PORTx I/O address, the PUExn bits at the PUEx I/O address, and the PINxn
bits at the PINx I/O address.
Pxn
1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same
port. clk
SLEEP:
clk
I/O
I/O
:
, and SLEEP are common to all ports.
SLEEP CONTROL
I/O CLOCK
SLEEP
51, the DDxn bits are accessed at the DDRx I/O address, the
(1)
SYNCHRONIZER
D
L
Q
Q
D
PINxn
Q
Q
RESET
RESET
RESET
PORTxn
WEx:
REx:
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
Q
Q
PUExn
DDxn
CLR
CLR
CLR
D
D
D
REx
RRx
WRITE PUEx
READ PUEx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Figure 10-2
WEx
WDx
RDx
RPx
clk
1
0
I/O
WRx
shows a func-
8127E–AVR–11/11
WPx

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