ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 56

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.3.2
11.4
56
Counter Unit
ATtiny4/5/9/10
External Clock Source
clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-
tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program
execution.
An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
a functional equivalent block diagram of the T0 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
parent in the high period of the internal system clock.
The edge detector generates one clk
6) edge it detects.
Figure 11-3. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 11-4 on page 57
Tn
clk
I/O
D
LE
Q
ExtClk
shows a block diagram of the counter and its surroundings.
Synchronization
D
< f
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
T
0
pulse for each positive (CS2:0 = 7) or negative (CS2:0 =
D
Figure 11-3 on page 56
Q
clk
I/O
Edge Detector
). The latch is trans-
clk_I/O
8127E–AVR–11/11
/2.5.
Tn_sync
(To Clock
Select Logic)
Tn
shows
). The