ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 69

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8127E–AVR–11/11
the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR0 (WGM03:0 = 8), or the value in OCR0A (WGM03:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT0 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on
quency correct PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in
the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent compare matches between OCR0x and TCNT0. The OC0x interrupt flag will be
set when a compare match occurs.
Figure 11-11. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x
Registers are updated with the double buffer value (at BOTTOM). When either OCR0A or ICR0
is used for defining the TOP value, the OC0A or ICF0 flag set when TCNT0 has reached TOP.
The interrupt flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x.
As
mode, symmetrical in all periods. Since the OCR0x Registers are updated at BOTTOM, the
length of the rising and the falling slopes will always be equal. This gives symmetrical output
pulses and is therefore frequency correct.
TCNTn
OCnx
OCnx
Period
Figure 11-11 on page 69
1
shows the output generated is, in contrast to the phase correct
Figure 11-11 on page
R
2
PFCPWM
=
3
log
---------------------------------- -
(
log
TOP
2 ( )
+
69. The figure shows phase and fre-
1
)
4
ATtiny4/5/9/10
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
69