ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 12

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.8
4.8.1
4.8.2
4.8.3
12
Register Description
ATtiny4/5/9/10
CCP – Configuration Change Protection Register
SPH and SPL — Stack Pointer Register
SREG – Status Register
• Bits 7:0 – CCP[7:0] – Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written
with the correct signature. After CCP is written the protected I/O registers may be written to dur-
ing the next four CPU instruction cycles. All interrupts are ignored during these cycles. After
these cycles interrupts are automatically handled again by the CPU, and any pending interrupts
will be executed according to their priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the pro-
tected feature is enabled, while CCP[7:1] will always read as zero.
Table 4-1
Table 4-1.
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the document “AVR Instruction
Set” and
Bit
0x3C
Read/Write
Initial Value
Bit
0x3E
0x3D
Read/Write
Read/Write
Initial Value
Initial Value
Bit
0x3F
Read/Write
Initial Value
Signature
0xD8
“Instruction Set Summary” on page
shows the signatures that are in recognised.
Signatures Recognised by the Configuration Change Protection Register
RAMEND
RAMEND
SP15
R/W
R/W
R/W
SP7
Group
IOREG: CLKMSR, CLKPSR, WDTCSR
W
7
0
15
7
0
I
7
RAMEND
RAMEND
SP14
R/W
SP6
R/W
R/W
W
T
6
0
14
6
0
6
RAMEND
RAMEND
R/W
SP13
SP5
R/W
R/W
W
13
H
5
0
5
0
5
RAMEND
RAMEND
SP12
R/W
R/W
R/W
SP4
W
4
0
12
4
S
0
152.
4
CCP[7:0]
RAMEND
RAMEND
SP11
R/W
SP3
R/W
R/W
W
3
0
11
3
V
0
3
RAMEND
RAMEND
SP10
R/W
SP2
R/W
R/W
W
10
N
2
0
2
0
2
Description
Protected I/O register
RAMEND
RAMEND
R/W
R/W
R/W
SP9
SP1
W
Z
1
0
1
0
9
1
RAMEND
RAMEND
R/W
R/W
SP8
SP0
R/W
R/W
C
0
0
0
0
8
0
8127E–AVR–11/11
SREG
CCP
SPH
SPL