ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 79

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.11.7
11.11.8
8127E–AVR–11/11
ICR0H and ICR0L – Input Capture Register 0
TIMSK0 – Timer/Counter Interrupt Mask Register 0
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See
The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the
ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bits 7:6, 4:3 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when the register is written.
• Bit 5 – ICIE0: Timer/Counter0, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Input Capture interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 66.) is executed when the
ICF0 Flag, located in TIFR0, is set.
• Bit 2 – OCIE0B: Timer/Counter0, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR0, is set.
• Bit 1 – OCIE0A: Timer/Counter0, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFR0, is set.
• Bit 0 – TOIE0: Timer/Counter0, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter0 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
Bit
0x23
0x22
Read/Write
Initial Value
Bit
0x2B
Read/Write
Initial Value
“Interrupts” on page
“Accessing 16-bit Registers” on page
R/W
R
“Accessing 16-bit Registers” on page
7
0
7
–
0
“Interrupts” on page
“Interrupts” on page
R/W
36) is executed when the TOV0 flag, located in TIFR0, is set.
R
6
0
6
–
0
R/W
ICIE0
R/W
5
0
5
0
R/W
36) is executed when the OCF0B flag, located in
36) is executed when the OCF0A flag, located in
4
0
R
4
–
0
ICR0[15:8]
ICR0[7:0]
72.
R/W
3
0
R
3
–
0
72.
OCIE0B
R/W
R/W
2
0
2
0
ATtiny4/5/9/10
OCIE0A
R/W
R/W
1
0
1
0
R/W
TOIE0
R/W
0
0
0
0
ICR0H
TIMSK0
ICR0L
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