ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 78

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.11.4
11.11.5
11.11.6
78
ATtiny4/5/9/10
TCNT0H and TCNT0L – Timer/Counter0
OCR0AH and OCR0AL – Output Compare Register 0 A
OCR0BH and OCR0BL – Output Compare Register 0 B
The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that the
FOC0A/FOC0B bits are implemented as strobes. Therefore it is the value present in the
COM0x1:0 bits that determine the effect of the forced compare.
A FOC0A/FOC0B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR0A as TOP.
The FOC0A/FOC0B bits are always read as zero.
• Bits 5:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when the register is written.
The two Timer/Counter I/O locations (TCNT0H and TCNT0L, combined TCNT0) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See
Registers” on page
Modifying the counter (TCNT0) while the counter is running introduces a risk of missing a com-
pare match between TCNT0 and one of the OCR0x Registers.
Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock
for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
Bit
0x29
0x28
Read/Write
Initial Value
Bit
0x27
0x26
Read/Write
Initial Value
Bit
0x25
0x24
Read/Write
Initial Value
R/W
R/W
R/W
7
0
7
0
7
0
72.
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
OCR1A[15:8]
OCR0B[15:8]
TCNT0[15:8]
OCR1A[7:0]
OCR0B[7:0]
TCNT0[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
“Accessing 16-bit
R/W
R/W
R/W
0
0
0
0
0
0
8127E–AVR–11/11
OCR0AH
OCR0AL
OCR0BH
OCR0BL
TCNT0H
TCNT0L