ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 104

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.5.3
14.5.4
14.5.5
104
ATtiny4/5/9/10
SSTPR - Serial STore to Pointer Register
SIN - Serial IN from i/o space using direct addressing
SOUT - Serial OUT to i/o space using direct addressing
where the address must have been stored before the operation. The Pointer Register can be
either left unchanged by the operation, or it can be post-incremented, as shown in
Table 14-3.
The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to
the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer
Register is accessed, as shown in
Table 14-4.
The SIN instruction loads data byte from the I/O space to the shift register of the physical layer
for serial read-out. The instuction uses direct addressing, the address consisting of the 6
address bits of the instruction, as shown in
Table 14-5.
The SOUT instruction stores the data byte that is shifted into the physical layer shift register to
the I/O space. The instruction uses direct addressing, the address consisting of the 6 address
bits of the instruction, as shown in
Table 14-6.
Operation
DS[PR]
DS[PR]
Operation
PR[a]
Operation
data
Operation
I/O[a]
←
←
←
←
←
I/O[a]
data
data
data
data
The Serial Store to Data Space (SLD) Instruction
The Serial Store to Pointer Register (SSTPR) Instruction
The Serial IN from i/o space (SIN) Instruction
The Serial OUT to i/o space (SOUT) Instruction
Opcode
0110 0000
0110 0100
Opcode
0110 100a
Opcode
0aa1 aaaa
Opcode
1aa1 aaaa
Table
Table
14-6.
14-4.
Table
Remarks
PR
PR
Remarks
Bit ‘a’ addresses Pointer Register byte
Remarks
Bits marked ‘a’ form the direct, 6-bit addres
Remarks
Bits marked ‘a’ form the direct, 6-bit addres
14-5.
←
←
PR
PR + 1
Register
Unchanged
Post increment
8127E–AVR–11/11
Table
14-3.