ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 37

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.2
9.2.1
9.2.2
8127E–AVR–11/11
External Interrupts
Low Level Interrupt
Pin Change Interrupt Timing
External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 or PCINT3..0 pins are configured as outputs.
This feature provides a way of generating a software interrupt. Pin change 0 interrupts PCI0 will
trigger if any enabled PCINT3..0 pin toggles. The PCMSK Register controls which pins contrib-
ute to the pin change interrupts. Pin change interrupts on PCINT3..0 are detected
asynchronously, which means that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as
shown in
enabled and configured as level triggered, the interrupt will trigger as long as the pin is held low.
Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O
clock, as described in
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source
can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in
all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined as described in
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction fol-
lowing the SLEEP command.
A timing example of a pin change interrupt is shown in
<continued>
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
...
“EICRA – External Interrupt Control Register A” on page
RESET: ldi
out
ldi
out
sei
<instr>
...
“Clock System” on page
r16, high(RAMEND); Main program start
SPH,r16
r16, low(RAMEND) ; to top of RAM
SPL,r16
17.
; Set Stack Pointer
; Enable interrupts
Figure
9-1.
38. When the INT0 interrupt is
“Clock System” on page
ATtiny4/5/9/10
17.
37