ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 57

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8127E–AVR–11/11
Figure 11-4. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT0L) containing the lower eight
bits. The TCNT0H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT0H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT0H value when the TCNT0L is read, and
TCNT0H is updated with the temporary register value when TCNT0L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT0 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, independent of
whether clk
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM03:0) located in the Timer/Counter Control Registers A and B (TCCR0A and TCCR0B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC0x. For more details about advanced counting
sequences and waveform generation, see
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM03:0 bits. TOV0 can be used for generating a CPU interrupt.
Count
Direction
Clear
clk
TOP
BOTTOM
TCNTnH (8-bit)
TEMP (8-bit)
T
0
TCNTn (16-bit Counter)
T
0
DATA BUS
is present or not. A CPU write overrides (has priority over) all counter clear or
TCNTnL (8-bit)
T
0
(8-bit)
). The clk
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock.
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
T
0
can be generated from an external or internal clock source,
Direction
Count
Clear
“Modes of Operation” on page
Control Logic
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
ATtiny4/5/9/10
Clock Select
( From Prescaler )
Detector
Edge
63.
Tn
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