ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 51

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.4
10.4.1
10.4.2
8127E–AVR–11/11
Register Description
PORTCR – Port Control Register
PUEB – Port B Pull-up Enable Control Register
Table 10-5.
Notes:
• Bits 7:2, 0 – Reserved
These bits are reserved and will always read zero.
• Bit 1 – BBMB: Break-Before-Make Mode Enable
When this bit is set the Break-Before-Make mode is activated for the entire Port B. The interme-
diate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see
Bit
0x03
Read/Write
Initial Value
Bit
0x03
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. EXT_CLOCK is 1 when external clock is selected as main clock.
Overriding Signals for Alternate Functions in PB1..PB0
PB1/ADC1/AIN1/OC0B/CLKI/ICP0/PCINT1
EXT_CLOCK
0
EXT_CLOCK
0
EXT_CLOCK
EXT_CLOCK
0
EXT_CLOCK
ADC1D
(EXT_CLOCK
(EXT_CLOCK
CLOCK/ICP0/PCINT1 Input
ADC1/Analog Comparator Negative Input
R
7
–
0
R
7
–
0
“Break-Before-Make Switching” on page
R
R
6
–
0
6
–
0
(1)
(1)
(1)
(1)
(1)
(1)
(1)
+ OC0B Enable
• OC0B
+ (PCINT1 • PCIE0) +
• PWR_DOWN) +
• PCINT1 • PCIE0)
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
PUEB3
R/W
3
0
R
3
–
0
43.
PB0/ADC0/AIN0/OC0A/PCINT0
0
0
0
0
OC0A Enable
OC0A
0
(PCINT0 • PCIE0) + ADC0D
PCINT0 • PCIE0
PCINT0 Input
ADC0/Analog Comparator Positive Input
PUEB2
R/W
2
0
R
2
–
0
ATtiny4/5/9/10
PUEB1
BBMB
R/W
R/W
1
0
1
0
PUEB0
R/W
R
0
0
0
–
0
PORTCR
PUEB
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