ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 30

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.3
30
Watchdog Timer
ATtiny4/5/9/10
30
reset time-out.
Figure 8-5.
The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See
6. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs.
Ten different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATtiny4/5/9/10 resets and executes from
the Reset Vector. For timing details on the Watchdog Reset, refer to
Figure 8-6.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
for details on operation of the Watchdog Timer and
CC
Table 8-2 on page
Watchdog Reset During Operation
Watchdog Timer
WATCHDOG
OSCILLATOR
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
33. The WDR – Watchdog Reset – instruction resets the Watchdog
CK
Table 16-4 on page 120
MCU RESET
PRESCALER
WATCHDOG
MUX
Table 8-3 on page
8127E–AVR–11/11
for details on
Figure 8-
34.