ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 80

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.11.9
11.11.10 GTCCR – General Timer/Counter Control Register
80
ATtiny4/5/9/10
TIFR0 – Timer/Counter Interrupt Flag Register 0
• Bits 7:6, 4:3 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when the register is written.
• Bit 5 – ICF0: Timer/Counter0, Input Capture Flag
This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register
(ICR0) is set by the WGM03:0 to be used as the TOP value, the ICF0 flag is set when the coun-
ter reaches the TOP value.
ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF0 can be cleared by writing a logic one to its bit location.
• Bit 2 – OCF1B: Timer/Counter0, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output
Compare Register B (OCR0B).
Note that a Forced Output Compare (0B) strobe will not set the OCF0B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF0A: Timer/Counter0, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output
Compare Register A (OCR0A).
Note that a Forced Output Compare (1A) strobe will not set the OCF0A flag.
OCF0A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF0A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV0: Timer/Counter0, Overflow Flag
The setting of this flag is dependent of the WGM03:0 bits setting. In Normal and CTC modes,
the TOV0 flag is set when the timer overflows. See
behavior when using another WGM03:0 bit setting.
TOV0 is automatically cleared when the Timer/Counter0 Overflow Interrupt Vector is executed.
Alternatively, TOV0 can be cleared by writing a logic one to its bit location.
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted.
Bit
0x2A
Read/Write
Initial Value
Bit
0x2F
Read/Write
Initial Value
TSM
R/W
7
0
R
7
–
0
R
R
6
–
0
6
–
0
ICF0
R/W
5
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
Table 11-5 on page 76
R
3
–
0
OCF0B
R/W
2
0
R
2
–
0
OCF0A
R/W
1
0
R
1
–
0
for the TOV0 flag
TOV0
R/W
PSR
0
0
R/W
0
0
8127E–AVR–11/11
TIFR0
GTCCR