ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 29

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8.2.3
8.2.4
8127E–AVR–11/11
External Reset
Watchdog Reset
The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the
Power-On Reset (POR) does not activate before supply voltage has dropped to a level where
the MCU is not necessarily functional any more. With VLM, it is possible to generate a reset
earlier.
When active, the VLM circuit consumes some power, as illustrated in
To save power the VLM circuit can be turned off completely, or it can be switched on and off at
regular intervals. However, detection takes some time and it is therefore recommended to leave
the circuitry on long enough for signals to settle. See
When VLM is active and voltage at V
normal and the VLM can be shut down for a short period of time. If voltage at V
the selected threshold the VLM will either flag an interrupt or generate a reset, depending on the
configuration.
When the VLM has been configured to generate a reset at low supply voltage it will keep the
device in reset as long as V
details. If supply voltage rises above the reset level the condition is removed and the MCU will
come out of reset, and initiate the power-up start-up sequence.
If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has
been restored.
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer
than the minimum pulse width (see section
will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to gen-
erate a reset. When the applied signal reaches the Reset Threshold Voltage – V
positive edge, the delay counter starts the MCU after the time-out period – t
External reset is ignored during Power-on start-up count. After Power-on reset the internal reset
is extended only if RESET pin is low when the initial Power-on delay count is complete. See
ure 8-2
Figure 8-4.
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the time-out period t
and
CC
Figure 8-3 on page
External Reset During Operation
CC
is below the reset level. See
28.
CC
is above the selected trigger level operation will be as
“System and Reset Characteristics” on page
“VCC Level Monitor” on page
Table 8-4 on page 35
ATtiny4/5/9/10
Figure 17-48 on page
TOUT
CC
TOUT
– has expired.
for reset level
120.
drops below
RST
. See
– on its
page
120)
147.
Fig-
29