ATtiny5 Atmel Corporation, ATtiny5 Datasheet - Page 85

• Manufacturer Part Number: ATtiny5
• Manufacturer: Atmel Corporation

Specifications of ATtiny5

• Flash (kbytes): 0.5 Kbytes
• Pin Count: 6
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 1
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 4
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 8
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.03
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.4
8127E–AVR–11/11
Starting a Conversion
Figure 13-1. Analog to Digital Converter Block Schematic
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power
Reduction Register, PRR (see
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in “ADCSRB – ADC Control and Status
Register B”. See
occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started.
This provides a method of starting conversions at fixed intervals. If the trigger signal still is set
when the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt
flag will be set even if the specific interrupt is disabled. A conversion can thus be triggered with-
out causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new
conversion at the next interrupt event.
ADC3
ADC2
ADC1
ADC0
V
CC
8-BIT DATA BUS
DECODER
ADMUX
Table 13-4 on page 96
INPUT
MUX
VREF
ADCSRB
“PRR – Power Reduction Register” on page
TRIGGER
SELECT
8-BIT DAC
for a list of the trigger sources. When a positive edge
PRESCALER
ADCSRA
CONVERSION LOGIC
SAMPLE & HOLD
COMPARATOR
-
+
ATtiny4/5/9/10
26).
ADCL
ADC IRQ
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