UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 59

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

3.2.3 Special function registers (SFRs)
LCDCTL in the LCD controller/driver.
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH areas in the CPU, and are allocated to the 00H to 03H areas of
Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit
Each manipulation bit unit can be specified as follows.
Table 3-6 gives a list of the special function registers. The meanings of items in the table are as follows.
1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, and
SM+, symbols can be written as an instruction operand.
R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
W:
Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “ ” indicates a bit unit for which manipulation is not possible.
After reset
Indicates each register status upon reset signal generation.
Read only
Write only
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18698EJ1V0UD
59