UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 133

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

5.6.4 Example of controlling internal low-speed oscillation clock
driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte.
5.6.5 Clocks supplied to CPU and peripheral hardware
of registers.
The internal low-speed oscillation clock cannot be used as the CPU clock.
Only the following peripheral hardware can operate with this clock.
In addition, the following operation modes can be selected by the option byte.
The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is
(1) Example of setting procedure when stopping the internal low-speed oscillation clock
(2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock
Caution If “Internal low-speed oscillator cannot be stopped” is selected by the option byte, oscillation of
The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting
Remarks 1. XSEL:
Internal high-speed oscillation clock
Internal high-speed oscillation clock
X1 clock
External main system clock
Subsystem clock
Watchdog timer
8-bit timer H1 (if f
LCD controller/driver (if f
Internal low-speed oscillator cannot be stopped
Internal low-speed oscillator can be stopped by software
<1> Setting LSRSTOP to 1 (RCM register)
<1> Clearing LSRSTOP to 0 (RCM register)
Clock Supplied to CPU
When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped.
When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted.
the internal low-speed oscillation clock cannot be controlled.
2. CSS:
3. MCM0: Bit 0 of MCM
4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL)
5.
Table 5-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting
:
RL
, f
RL
Bit 2 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
don’t care
/2
RL
7
/2
or f
Supplied Clock
3
RL
is selected as the LCD source clock)
/2
9
Clock Supplied to Peripheral Hardware
X1 clock
External main system clock
Internal high-speed oscillation clock
X1 clock
External main system clock
is selected as the count clock)
CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
XSEL
0
1
1
1
1
0
1
1
1
1
CSS
0
0
0
0
0
1
1
1
1
1
MCM0
0
0
1
1
0
1
0
1
EXCLK
0
1
0
1
0
0
1
1
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