UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet - Page 466

• Manufacturer Part Number: UPD78F0413GA-GAM-AX
• Description: 8BIT UC, 32K FLASH, 1KB RAM, LCD
• Manufacturer: NEC

Specifications of UPD78F0413GA-GAM-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 30
• Ram Memory Size: 1024Byte
• Cpu Speed: 10MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 32KB
• Oscillator Type: External, Internal

Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
(2) STOP mode release
466
Note
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
2. Even if “internal low-speed oscillator can be stopped by software” is selected by the option
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
The wait time is as follows:
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillator’s oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the next execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
Figure 19-5.
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is not carried out: 2 or 3 clocks
STOP mode
STOP mode release
Operation Timing When STOP Mode Is Released (When Unmasked Interrupt
Request Is Generated)
Wait for oscillation accuracy
(oscillation stabilization time set by OSTS)
stabilization (86 to 361 s)
CHAPTER 19 STANDBY FUNCTION
Wait
Wait
Internal high-speed
Note
Note
HALT status
User’s Manual U18698EJ1V0UD
oscillation clock
High-speed system clock
8 or 9 clocks
Clock switched by software
Automatic selection
High-speed system clock
High-speed system clock