ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 807

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

41.5
41.5.1
32058J–AVR32–04/11
Rev. E
SPI
1. SPI FDIV option does not work
2. SPI Slave / PDCA transfer: no TX UNDERRUN flag
3. SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and
4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first
5. SPI CSNAAT bit 2 in register CSR0...CSR3 is not available.
6. SPI disable does not work in SLAVE mode.
7. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and
Selecting clock signal using FDIV = 1 does not work as specified.
Fix/Workaround
Do not set FDIV = 1.
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
CNCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others
doesn’t equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on
SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrate equals to 1, the other must also equal 1
if CPOL=1 and CPHA=0.
transfer
In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or
during the first transfer.
Fix/Workaround
1. Set slave mode, set required CPOL/CPHA.
2. Enable SPI.
3. Set the polarity CPOL of the line in the opposite value of the required one.
4. Set the polarity CPOL to the required one.
5. Read the RXHOLDING register.
Transfers can now befin and RXREADY will now behave as expected.
Fix/Workaround
Do not use this bit.
Fix/Workaround
Read the last received data, then perform a Software Reset.
NCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't
equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
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