ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 395
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 395 of 826
- Download datasheet (20Mb)
27.6.7.3
Figure 27-29. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11).
32058J–AVR32–04/11
In te rn a lly s y n c h ro n iz e d
N W A IT s ig n a l
N B S 0 , N B S 1 ,
C L K _ S M C
A 0 , A 1
A [2 5 :2 ]
N W A IT
D [1 5 :0 ]
Ready Mode
N C S
N W E
6
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure
27-30.
4
5
4
3
3
2
1
2
E X N W _ M O D E = 1 1 (R e a d y m o d e )
W R IT E _ M O D E = 1 (N W E _ c o n tro lle d )
N W E _ P U L S E = 5
N C S _ W R _ P U L S E = 7
W rite c y c le
0
1
F R O Z E N S T A T E
0
1
Figure 27-29
0
1
0
and
AT32UC3A
Figure
27-30. After
Fig-
395
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