ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 783
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 783 of 826
- Download datasheet (20Mb)
Table 38-30. SPI Timings
Notes:
38.12 MACB Characteristics
Table 38-31. Ethernet MAC Signals
Notes:
Table 38-32. Ethernet MAC MII Specific Signals
32058J–AVR32–04/11
Symbol
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
Symbol
EMAC
EMAC
EMAC
Symbol
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
EMAC
0
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
1. 3.3V domain: V
2. t
1. f: MCK frequency (MHz)
2. V
CPMCK
VDDIO
Parameter
MISO Setup time before SPCK rises (master)
MISO Hold time after SPCK rises (master)
SPCK rising to MOSI Delay (master)
MISO Setup time before SPCK falls (master)
MISO Hold time after SPCK falls (master)
SPCK falling to MOSI Delay (master)
SPCK falling to MISO Delay (slave)
MOSI Setup time before SPCK rises (slave)
MOSI Hold time after SPCK rises (slave)
SPCK rising to MISO Delay (slave)
MOSI Setup time before SPCK falls (slave)
MOSI Hold time after SPCK falls (slave)
: Master Clock period in ns.
Parameter
Setup for EMDIO from EMDC rising
Hold for EMDIO from EMDC rising
EMDIO toggling from EMDC falling
Parameter
Setup for ECOL from ETXCK rising
Hold for ECOL from ETXCK rising
Setup for ECRS from ETXCK rising
Hold for ECRS from ETXCK rising
ETXER toggling from ETXCK rising
ETXEN toggling from ETXCK rising
ETX toggling from ETXCK rising
Setup for ERX from ERXCK
from 3.0V to 3.6V, maximum external capacitor = 20 pF
VDDIO
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Load: 20pF
Conditions
Conditions
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
3.3V domain
Conditions
(2)
(2)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
22 + (t
22 + (t
Min (ns)
Min (ns)
Min
CPMCK
CPMCK
1.5
0
0
0
0
1
3
0
3
0
1
)/2
)/2
(2)
(2)
AT32UC3A
Max
26.5
27
7
7
Max (ns)
Max (ns)
15
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
783
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